An FPGA-based Floating Point Unit for Rounding Error Analysis

نویسندگان

  • Michael Frechtling
  • Philip H.W. Leong
چکیده

Detection of floating-point rounding errors normally requires run-time analysis in order to be effective and software-based tools are seldom used due to the extremely high computational demands. In this paper we present a field programmable gate array (FPGA) based floating-point coprocessor which supports standard IEEE-754 arithmetic, user selectable precision and Monte Carlo Arithmetic (MCA). This co-processor enables the detection of catastrophic cancellation and minimizing required floating-point precision in reconfigurable computing applications

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تاریخ انتشار 2013